Dynamic random access memories comprise a multiplicity of row and column addressable memory cells. Each memory cell comprises a capacitor and an insulated-gate field-effect (IGFET) access transistor. The capacitor is coupled to a column line (also referred to as either a digit line or a bit line) through the access transistor, the gate of which is controlled by a row line (also referred to as a word line). A binary bit of data is represented by either a charged cell capacitor (a binary 1) or an uncharged cell capacitor (a binary 0). In order to determine the contents of a particular memory cell, the word line associated with that memory cell is activated, thus shorting the cell capacitor to the digit line associated with that particular cell. It has become common to "bootstrap" the word line to a voltage greater than the power supply voltage (V.sub.CC) so that the full charge (or lack of charge) in the cell is dumped to the digit line. Prior to the read operation, the digit lines are equilibrated to V.sub.CC /2. Thus, when a cell capacitor is shorted to its respective digit line, the equilibration voltage is either bumped up slightly by a charged capacitor or pulled down slightly by a discharged capacitor. Once full charge transfer has occurred between the digit line and the cell capacitor, sense amplifiers associated with the digit line are activated in order to latch the date. The latching operation may be described as follows: If the resulting digit line voltage is less than V.sub.CC /2, an N-channel sense amplifier pulls the digit line to ground potential; conversely, if the resulting digit line voltage is greater than V.sub.CC /2, a P-channel sense amplifier line raises the voltage on the digit line to a full V.sub.CC.
Timing of the latching operation is critical. If latching takes place before full charge transfer has occurred, the latched values may not reflect the true data value of stored data bit. On the other hand, if latching takes place too long after full charge transfer has occurred, the charge on the digit line will partially dissipate and the latched value may not reflect the true value of the stored data bit. Even if the data is not inaccurately latched, the operational speed of the memory will suffer. On thing is clear. Clearly, there is an optimum moment for the latching of data in a dynamic random access memory. The more closely the latching operations coincide with that optimum moment, the more sound the operational characteristics of the memory.
Present-day technology typically employs a series of delay elements or a Schmidt trigger in combination with dummy memory array elements (which provide an approximation of the RC time constant of the actual memory array) to approximate the optimum moment for latching. In this disclosure, a compact sense circuit is disclosed which more accurately tracks charge transfer between the capacitor of a dynamic random access memory cell and its associated digit line.